Analog Circuit Design for Communication SOC

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System-on-a-Chip (SOC) refers to integrating all components of a computer or other electronic systems into a single integrated circuit. It may contain digital, analog, mixed-signal, and often radio-frequency functions for communications – all on one chip. SOC is believed to be more cost effective since it increases the yield of fabrication and reduces packaging efforts. Presently, the bottleneck of SOC developments is the interfaces among its sub-functional blocks since an SOC system comprises a variety of different functional blocks such as DSP, memories, microprocessors, wireless communication circuits, wired communication circuits, system timing generators, data converters, voltage regulators. Because of the integration of different fabrication-technology circuits for different functional blocks on the same chip, the circuit design of internal signal interfaces between analog and digital circuits, low-frequency logic circuits and high-frequency communication circuits can be a tough challenge especially its analog circuit design since the analog circuits for communication are more sensitive to noise interference, temperature and process variations. The analog circuit design techniques for communication SOC, which enable a larger design tolerance while maintaining the simplicity of the circuits are therefore highly desired.

Mixer is a kind of circuit in which two signals are ‘mixed’ to produce desired difference or sum frequencies, which is employed for a wireless communication system to down/upconvert the input signal to a much lower / higher carrier frequency than the input RF signal. To enrich the background knowledge, a comprehensive fundamental of mixer will be firstly presented in sections 1 and 2. General design considerations will be then described. Several configurations of mixer circuits will be addressed in section 4. To summarize the chapter, a case study concerned with a 5.26-GHz CMOS up-conversion mixer for IEEE 802.11a WLAN will be described in the final section

With the progress of submicron MOS technologies, recent efforts in the design of wireless transceivers have focused on achieving higher levels of integration compared with conventional approaches. As a result, CMOS may prove to be a feasible technology to attain the goal of full-scale integration. This chapter will investigate the design and implementation of wireless power amplifiers in CMOS technology, which we mainly investigate the class-AB “linear” power amplifier and the class-E “nonlinear” power amplifier for the applications of different modulation schemes. The practical considerations for the implementation will be presented in the case study concerned with the implementation of an experimental prototype test chip fabricated in a 0.18-µm CMOS process.

Phase-Locked Loops (PLLs) are widely used in wired/wireless communication systems, disk drive electronics, high-speed digital circuits, and instruments to deal with frequency synthesizing, clock multiplication and synchronization issues. Although the first PLL was realized in 1932 by Bellesize, a French engineer, the broader industrial applications were seen only when the monolithic IC implementation was available in 1965. The characteristic of clock multiplication makes PLLs irreplaceable in modern wireless communication systems. However, the major consideration for the design of a PLL is the stability issue due to the extra pole contributed by the oscillator. Hence the role which PLLs play for clock synchronization in modern IC design is gradually replaced by delay-locked loops (DLLs) in recent years. Due to the difference of their configurations, DLLs are preferred for their unconditional stability and less lock time than PLLs. Additionally, DLLs offer better jitter performance than PLLs do because the noise in the voltage-controlled delay line (VCDL) does not accumulate with time. The other important role for PLLs is the clock/data recovery (CDR) circuit in wired-line communication systems. The CDR circuit was first realized based on a simple PLL with additional devices and is now developed to be an individual category for the phase locking techniques.

The demand of the fast information exchanging has become the motive of communication revolutions. In recent years, the increase of data transmission over the internet has led to the demand for high-speed serial-data communication networks. Considerable design efforts have been focused on low-cost, low-power integrated transmitters and receivers. Several optical communication standards have been applied to high-speed and longdistance communications. With the aid of wave-length division multiplexing technique, several optical communication systems, such as SDH/SONET and 10G-Based Ethernet, allow the information to be exchanged with different bit rates at the same time in the optical domain. On the other hand, the advancement of the multimedia environment in personal computer (PC) has brought out lots of business opportunities in the PC peripherals. PC has changed its identity to be the most popular platform for multimedia. Many commercial products provide a friendly way for file transferring via either the universal serial bus (USB) or the IEEE 1394 FireWire interface. In this chapter, the basics for wired-line communications would be introduced first. The details of the DLL-based clock generation technique for the transmitter would be examined. The design issues of the clock/data recovery technique for the receiver would be explored as well.

This chapter outlines the fundamental performance metrics and the dynamic characteristics of data converters. Nyquist-rate data converters which appropriately apply in the utilization of modern communications are introduced. The Nyquist-rate DAC, such as resistor string DAC, binary-weighted resistor DAC, charge redistribution DAC, and current steering DAC, are illustrated. And the Nyquist-rate ADC, such as flash ADC, folding ADC, two-step ADC, and pipelined ADC, are presented.

This chapter introduces the principles and composition of oversampling data converters. Firstly, the concepts and noise reduction of oversampling data conversion are demonstrated. Then the topologies of various order delta-sigma modulator are presented. Finally, the signal processing procedure, including decimation and interpolation filters are characterized.

This chapter presents a comprehensive introduction and fundamentals of design techniques for switching-mode digital pulse-width modulation (DPWM) power regulators. The presented switching-mode regulation approach inspires several novel building functional blocks such as error process unit (EPU), multipleaccess table look-up based PID compensator, and multi-phase digital PWM. Compared with the conventional architecture with an analog-to-digital converter, the new switching-mode configuration can reduce the system complexity. The practical considerations for the implementation will be presented in the case study concerned with a fully table look-up digital PWM controller for high-frequency power regulation.

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